1. Field of the Invention
This invention relates to a metal oxide semiconductor transistor and a fabrication method thereof, and more particularly relates to a trench metal oxide semiconductor transistor and a fabrication method thereof.
2. Description of Related Art
In order to catch up the requirements of power saving and low energy loss, converters with higher power conversion efficiency, which brings the circuit designers a more severe challenge, are unpreventable. To overcome this challenge, the newly developed power elements play an important role. In present, the power metal oxide semiconductor field effect transistor (MOSFET) has been widely adopted to various power converters.
Energy loss of the power metal oxide semiconductor field effect transistor (MOSFET) includes conduction loss resulted from on-resistance and energy loss resulted from inter-electrode capacitance (including output capacitance Ciss and reverse transfer capacitance Crss). It is noted that energy loss other than the conduction loss resulted from the on-resistance is positive correlated to the inter-electrode capacitance and the operation frequency of the power MOSFET. Therefore, in order to increase the operation frequency, the inter-electrode capacitance of the power MOSFET should be reduced so as to prevent the increasing of energy loss.
FIGS. 1A to 1H are schematic views showing the fabrication method of a typical trench power MOSFET. An N-type power MOSFET is taken for example. As shown in FIG. 1A, an N-type epitaxial layer 120 is firstly formed on an N-type silicon substrate 110. Then, the location of gate trenches 130 is defined by using a mask and the dry etching process is carried out to form a plurality of gate trenches 130 in the epitaxial layer 120.
Afterward, referring to FIG. 1B, a gate oxide layer 140 is formed to line the inner surface of the gate trench 130. Then, a polysilicon layer is deposited over all the exposed surfaces of the epitaxial layer 120 and fills the gate trenches 130. Thereafter, the etching back process is carried out to remove polysilicon material above the gate trenches 130 so as to form polysilicon gates 152 resided in the gate trenches 130. It is noted that, the upper surface of the polysilicon gate 152 is located below the upper edge of the gate trenches 130 due to the etching back process.
Afterward, referring to FIG. 1C, P-type impurities are implanted to the N-type epitaxial layer 120 by ion implantation and an implanted surface region 120a is shown. Then, referring to FIG. 1D, a thermal drive-in process is introduced to diffuse the P-type impurities to form a P-well 122 in the N-type epitaxial layer 120. It is noted that of the epitaxial layer 120 near the gate trench 130, both the upper surface and the sidewall are exposed to the implanted P-type impurities. Thus, referring to FIG. 1C, implant depth and concentration of the epitaxial layer 120 near the gate trench 130 is greater than the other portion of the epitaxial layer 120. As a result, after the drive-in step, the profile of the P-well 122 shows greater depths at the center 122a and the two edges 122b adjacent to the gate trenches 130.
Afterward, referring to FIG. 1E, a photo-resist pattern 162 for defining the source is formed on the epitaxial layer 120 by using a source mask (not shown). Then, N-type impurities are implanted to the P-well 122 by ion implantation to form a plurality of N-type source regions near the exposed surface of the P-well 122 and adjacent to the sidewalls of the gate trenches 130.
Thereafter, referring to FIG. 1F, a dielectric layer 170, such as a BPSG layer, is deposited over all the exposed surfaces to cover the polysilicon gates 152, the source regions 160, and the exposed P-well 122. Then, a contact window 172 is formed in the dielectric layer 170 by using lithography and etching process to expose the source regions 160 and the P-well 122.
Thereafter, referring to FIG. 1G, P-type impurities are implanted through the contact window 172 to the P-well 122 to form a P-type heavily doped region 180 at the upper portion of the P-well 122. Finally, referring to FIG. 1H, a metal layer 190 is deposited over the dielectric layer 170 and fills the contact window 172 to cover the source region 160 at the bottom of the contact window 172.
However, referring to FIGS. 1C and 1D, because the epitaxial layer 120 has higher impurity concentration and greater implantation depth near the gate trenches 130, the profile of the P-well 122 must have greater depths at the both edges 122b adjacent to the gate trenches 130. Such impurity distribution is bad for implant profile control. The bottom of the gate trenches 130 should be connected to the N-type epitaxial layer 120 under the P-well 122. Because the epitaxial layer 120 has a higher impurity concentration and a greater implantation depth near the gate trenches 130, it is hard to control the diffusion of P-type impurities during the drive-in step to expand the P-type region downward and prevent the bottom of the gate trenches 130 from being covered by the P-well 122 at the same time.
Accordingly, how to improve the depth profile of the well of the metal oxide semiconductor field effect transistor to prevent the bottom of the gate trenches from being covered by the well to result in failure is a topic eager to be resolved.